Optimal Transistor Level Budgeting Method for Power Optimization

 This paper presents an optimal budget distribution method for low power circuit design using transistor sizing. The algorithm distributes the available budget on the transistors optimally by an efficient traversal of the Series Parallel Graph representations of functional units. The technique can be efficiently applied at different abstraction levels of the design as well as toward other optimization goals (such as area optimization). Incorporating our method in the design flow yields significant improvements in power consumption. Experiments on circuits extracted from MCNC91 benchmark suite have revealed improvements up to 59% in average power and 65% in maximum power dissipation compared to alternative budget distribution algorithms.